Peak, Period and Duty-Cycle Detector Overview
The Peak, Period and Duty-Cycle Detector LSIP is used for analysing standing pulse waveforms with relatively stable frequencies and duty-cycles. The IP continuously computes the Phase1 (high duration) and Phase1 (low duration) periods, as well as the average amplitudes across specific windows during the Phase1 and Phase2 of the input waveform.
For period detection, the 50% cross-over thresholds of the rise and fall transitions are first determined using the input peak values. These cross-over threshold numbers are stabilized using a moving average block, before feeding to the period detection logic. The period detection logic in turn uses these stabilized thresholds to count the periods. The resultant Phase1/Phase2 period-counts are further stabilized using another moving average block, before feeding to the MMR register block.
The IP has been fully validated for input signal frequencies up to 100KHz and 250MSPS sample-rate on XILINX Zynq7000 series 28nm AP-SOC (ARM+FPGA).
Typical applications of the Peak, Period and Duty-Cycle Detector LSIP:
- RF Envelope Analysis : Can be used in applications were the envelope amplitude/frequencies of pulsed RF waveforms need be detected.
- Test and Measurement : Can be deployed for analysing the properties of low frequency (compared to clock-rate) square/pulsed wave sources.
Variable Parameters of the Peak, Period and Duty-Cycle Detector LSIP:
- Generation-time configurable (using SParrow) : Input sample width, Moving Average counts.
- Run-time programmable (AXI4-Lite access) : None.
Key Features of the Peak, Period and Duty-Cycle Detector LSIP :
- The Peak Detection windows (for both Phase1 and Phase2 of the input pulse-waveform) can be specified using either an external synchronizing pulse input or by using the inbuilt automated window detection logic.
- The IP can dynamically adapt to changing peak and frequency values of the input waveform, so long as the changes stabilizes in a few cycles.
- For a typical input signal frequency of 1KHz and sample-rate (same as clock-rate) of 250MSPS, the IP has been proven to yield better than 0.02% accuracy with frequency/duty-cycle detection. The accuracy of peak detection depends up on the ripples and averaging counts.
- Peak and Period detection results are captured in Read-Only Memory Mapped Registers, which can be accessed using a standard AXI4-Lite interface. A Lock-Bit functionality is also provided to prevent update of the result registers during bulk read operations.
Peak, Period and Duty-Cycle Detector – High Level Block Diagram.
Peak, Period and Duty-Cycle Detector – Data Capture from Lab Characterization