LSIPs – Overview
Logosent SParrow DSP IP blocks (LSIPs) are fully configurable off-the-shelf DSP functionality that can be directly deployed in various DSP systems based on FPGAs, AP-SOCs and ASICs, eliminating the need for grounds-up development and validation overheads. The LSIPs provide highest flexibility to the users in terms of configurability and run-time programmability, while yielding the best performance possible in terms of RTL timing closure and data throughput.
The LSIPs are generated using the Logosent SParrow tools and DSP libraries. Each LSIP packages include:
-
- A reference design with fully synthesizable RTL code and the software algorithms corresponding to the LSIP functionality, for a default configuration.
- An RTL testbench with typical test-cases that can be used to simulate the LSIP RTL at the user end, if needed. These testbenches can be easily reconfigured to match new configurations of the LSIP that the users may need to generate.
- All required driver software code, build-scripts and implementation constraints that are needed to implement the system in standard FPGA/AP-SOC prototyping platforms like XILINX® Zynq based ZedBoard.
- A custom version of the Logosent SParrow tool optimized for the each LSIP, which can be installed on the user machine. Using this SParrow version, the LSIP users can regenerate the IP RTL/C code to match specific end-application requirements
- Detailed user manual and 1-year technical support to help the users reconfigure the LSIPs (if needed) and/or seamlessly integrate the LSIPs into their systems.
All LSIPs are pre-Verified for accuracy against MATLAB® models, taken through rigorous RTL simulations and fully validated at high Sample/Clock rates on FPGA/AP-SOC platforms like XILINX® Zynq based ZedBoard.
Our Differentiation – Hardware IPs
- A rich set of leaf-library components and composite IPs optimized to address the needs of various DSP domains like RF, Test & Measurement, Audio and Sensors.
- Highly performance-optimized RTL to achieve the best clock-rates in mapping to ASIC or FPGA. (Proven up to 250MHz/250MSPS operation in XILINX® Zynq7000 series 28nm FPGAs)
- Uniquely pipelined architecture for supporting input sample-rate equal to the functional clock-frequency, even for complex arithmetic operations like square-root and division.
- Specially coded RTL to facilitate direct mapping of arithmetic functions to pre-defined MAC structures like DSP-Slices in FPGAs and ASIC libraries.
- Proprietary streaming bus architecture for seamless connectivity (zero glue-logic, zero clock-cycle loss) between individual components, with full data-throttling and AXI4 external i/f support.
- All Hardware IPs and Sub-Systems qualified through a three-stage V&V process:
- Extensive RTL simulations.
- Bit-accuracy comparisons against MATLAB/C models.
- At-speed validation on FPGA platforms integrating High-Speed signal sources.
Optimized Fixed-Point C Algorithms for achieving lowest compute-resource utilization
- Generic DSP Algorithms including:
- Sources – Sine, Chirp, White/Colour Noise, AM, FM, etc.
- Filters – Generic FIR, IIR, etc.
- Multi-rate FIR, Half-band IIR, CIC, etc.
- DDC, DUC, DSS, etc.
- FFT and related transformations, like Zoom-FFT, CZT, etc.
- Dynamic processing, Windowing and filtering.