AD9467 ADC An Introduction

  • Features

    • 75.5 dBFS SNR to 210 MHz at 250 MSPS, 90 dBFS SFDR to 300 MHz at 250 MSPS, SFDR at 170 MHz at 250 MSPS.
    • 92 dBFS at −1 dBFS, 100 dBFS at −2 dBFS, 60 fs rms jitter.
    • Excellent linearity at 250 MSPS.
    • 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable).
    • Integrated input buffer.
    • External reference support option.
    • Clock duty cycle stabilizer, Output clock available.
    • Serial port control.
    • Built-in selectable digital test pattern generation.
    • Selectable output data format.
    • LVDS outputs (ANSI-644 compatible).
    • 1.8 V and 3.3 V supply operation.
  • EVAL Board available : AD9467-FMC-250EBZ
  • ADI Reference Page: https://www.analog.com/en/products/ad9467.html#product-overview

SParrow® support for AD9467

  • SParrow®-AD9467 Version generates Verilog RTL IPs, C++ algorithms and C++ framework code required to interface AD9467-FMC-250EBZ EVAL Board with XILINX® ZC706 or AVNET® ZedBoard.
  • All TCL files and constraints required to implement the system using XILINX Vivado® tool are also auto-generated by SParrow®, so that the bit-stream can be generated directly from the RTL/C Code.
  • The main RTL components that are integrated into SParrow® for AD9467 support on FPGA board include:

    • AD9467 Interface : An RTL Component that interfaces with the FMC connector of AD9467-FMC-250EBZ EVAL Board.
    • RASTER NCO IP : A LUT based NCO that can be used for generating mathematically accurate Sinusoidal waveforms.
    • LINEAR WAVEGEN IP : Generates various types of square, saw-tooth, triangular, trapezoidal and other linear waves.
    • Basic DSP/MISC RTL IPs like ADDER, MULTIPLIER, MIXER/MODULATOR, FIR FILTER, MUX, GATES, TIMER, MMRs etc.

SParrow® – AD9467 System Architecture

Supported Eval Board + FPGA Board Pair

Reference Design RF Envelop Extractor